Iker Garcia Morales | Electrical Engineering

Featured Work

MIPS8 Processor.

A complete 8-bit processor designed from transistor-level schematics to verified layout.

Full-custom layout in Electric VLSI Verified with DRC, ERC, NCC, and IRSIM Built around a custom MIPS8 assembly flow

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Selected Work

Projects.

VLSI / Layout

MIPS8 Processor

Full-custom 8-bit processor built from schematics to verified layout.

Electric VLSIIRSIMLayout

DRC/ERC/NCC checkedFull-custom layout

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ASIC / Digital Logic

Similarity Detector

Vector similarity circuit using XNOR matching, popcount logic, and threshold comparison.

VerilogASICLogic Design

Custom datapathVerified logic

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PCB Design

Cansat Flight Computer PCB

Mission-tested flight computer PCB for sensing, telemetry, and fast debugging.

ESP32LoRaKiCad

Competition testedTelemetry validated

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PCB Design

Low Voltage Disconnect PCB

Battery protection board that disconnects the load below a safe voltage threshold.

PCBPowerProtection

Tested cutoff behaviorBattery protection

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Me

Building custom silicon.

Hey, I’m Iker Garcia Morales, a Walton International Scholarship recipient at John Brown University pursuing a double major in Electrical Engineering and Robotics & Mechatronics Engineering.

My work focuses on integrated circuit design, VLSI, and computer architecture, with the goal of understanding and building systems from the transistor level up.

I’m passionate about open-source technology because I believe the best ideas grow when people build, learn, and share knowledge together.

What I work on

Technical Focus.

01

VLSI & Chip Design

Integrated circuits, transistor-level design, layout, and verification.

02

PCB Development

Practical boards built around debugging, reliability, and fast iteration.

03

Computer Architecture

Processor design, instruction set development, datapath organization, and digital systems.

Skills & Tools

Tools I use.

Electric VLSI IRSIM SystemVerilog Verilog KiCad EasyEDA ESP-IDF Git GitHub MATLAB

In Progress

Currently Building.

Silicio-16.

A custom 16-bit CPU architecture designed from ISA design to FPGA implementation.

Silicio-16 is currently in the datapath architecture stage. The current focus is defining how registers, control flow, memory access, and execution units connect before moving into simulation and RTL implementation.

ISA design Datapath architecture Simulator / assembler RTL implementation Verification FPGA implementation Silicon exploration

Datapath architecture 15%

Datapath

Perceptron.

A small hardware neural layer made of 4 digital perceptrons working in parallel.

This project started as research, but it is now entering the first Verilog implementation stage. The current goal is to build, simulate, and understand a simple 4-perceptron layer before improving the architecture. Each perceptron computes a weighted sum from the input bits, compares it against a threshold, and produces one output bit.

Research Single perceptron prototype 4-perceptron layer Verilog simulation Testbench and waveform validation Portfolio case study

Early HDL implementation 15%

Early HDL

Notes & Ideas