IGM Iker Garcia Morales

Computer Architecture / RTL

Silicio-16.

A compact 16-bit processor built from first principles.

Silicio-16 is a custom multicycle CPU designed in SystemVerilog. The project explores a complete small processor flow: custom ISA design, RTL datapath implementation, control sequencing, memory behavior, and verification through simulation waveforms.

SystemVerilog 16-bit Multicycle Custom ISA
GitHub repository Documentation Open Simple Silicon Back to portfolio
Current status Framebuffer / Graphics Demo
Overall progress 70%
Real Simple Silicon waveform capture of the Silicio-16 Fibonacci program showing memory writes and datapath activity.
Real execution waveform from the Silicio-16 simulation artifacts.

Overview

Silicio-16 is a compact 16-bit processor project built to understand how a CPU moves from instruction set design into hardware execution. The goal is not to make a large processor, but to build a clear one: small enough to reason about, complete enough to execute real programs, and structured enough to keep growing.

The project currently includes a custom ISA, a multicycle RTL datapath, a finite-state control unit, separate instruction and data memory, regression testing, and program-level simulations. Current work is focused on framebuffer and graphics demos before future FPGA integration.

Architecture & Datapath

Processor structure.

Data width16-bit
Instruction width16-bit
Registers8 general-purpose
Execution modelMulticycle
ISACustom
MemorySeparate instruction and data memory
Silicio-16 datapath schematic showing the program counter, instruction register, register file, ALU, memory paths, and control signals.
Datapath schematic from the Silicio-16 architecture documentation.

The datapath connects the program counter, instruction register, register file, A/B operand registers, ALU, ALU output register, immediate extension, memory data register, and flags register. These blocks form the path used by arithmetic, memory, and control-flow instructions.

A centralized finite-state control unit sequences each instruction across multiple cycles. This keeps the processor small and readable while still allowing instruction fetch, decode, execute, memory access, and writeback behavior to happen in a controlled order.

Silicio-16 uses separate instruction and data memory. Instruction memory feeds the fetch path, while data memory supports LOAD and STORE behavior through the memory data register and ALU-generated addresses.

The current ISA includes arithmetic, bitwise, comparison, move, immediate, memory, branch, jump, and halt instructions. The regression suite checks the main behavior across these instruction families. 

NOP ADD SUB AND OR XOR SIM MOV LDI LOAD STORE CMP BEQ BNE JMP HALT

Verification & Waveforms

Simulation evidence.

These entries use real Simple Silicon waveform screenshots captured during Silicio-16 verification.

This capture checks the ADD execution path and shows the ALU result moving through the processor datapath during the test.

Real Simple Silicon waveform capture for the Silicio-16 ADD test.
ADD Test: validates arithmetic result propagation through the ALU path.

The memory test stores a register value into data memory and loads it back into another register. This validates the address path, memory write control, memory data register, and register writeback behavior.

Real Simple Silicon waveform capture for the Silicio-16 load and store test.
Load & Store Test: confirms memory data can be written and read back through the CPU path.

Flow-control testing covers program counter updates through jump, NOP, halt stability, and branch offset behavior. The waveform keeps the focus on PC movement and instruction sequencing.

Real Simple Silicon waveform capture for Silicio-16 flow control.
Flow Control: shows program counter movement through the control path.

Conditional-flow tests include BEQ and BNE cases where the branch is taken and not taken. The regression also includes a negative branch offset case to check signed control-flow behavior.

Real Simple Silicon waveform capture for Silicio-16 conditional flow control.
Conditional Flow Control: validates conditional PC updates and control sequencing.

This test loads 12 and 5 into R1 and R2, executes SUB, AND, OR, and XOR, stores the results in R3 through R6, and ends with HALT.

Real Simple Silicon waveform capture for Silicio-16 ALU Test 1 basic operations.
ALU Test 1: proves the basic arithmetic and bitwise operation paths.

This test loads 0x00FF and 0x000F, executes the custom SIM instruction, copies the result with MOV, and ends with HALT.

Real Simple Silicon waveform capture for Silicio-16 ALU Test 2 SIM and MOV.
ALU Test 2: verifies the custom SIM instruction and MOV result transfer.

This test loads R1 = 5 and R2 = 10, uses CMP and BNE to skip address 4, uses JMP to skip address 6, and reaches HALT at address 7.

Real Simple Silicon waveform capture for Silicio-16 reverse conditional flow and halt.
Reverse Conditional Flow and Halt: checks branch decisions, jump behavior, and final HALT sequencing.

This is the strongest system-level demonstration because it combines arithmetic, looping, register operations, control flow, and memory writes.

Real Simple Silicon waveform capture for the Silicio-16 Fibonacci program.
Fibonacci Program: system-level execution with arithmetic, loop control, registers, and memory writes.

Project Roadmap

Where it stands.

Architecture & ISAComplete
Datapath RTLComplete
RTL Bring-UpComplete
First Program ExecutionComplete
Full ISA VerificationComplete
Framebuffer / Graphics DemoCurrent
FPGA IntegrationUpcoming
Silicon ExplorationFuture
Overall project progress 70%